circuit BoomDuplicatedDataArray :
  module BoomDuplicatedDataArray : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip read : {valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[1], flip write : {valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<1>, data : UInt<64>}}, resp : UInt<64>[4][1], nacks : UInt<1>[1]}
    
    clock is invalid
    reset is invalid
    io is invalid
    node waddr = shr(io.write.bits.addr, 3) @[dcache.scala 277:34]
    node _T = shr(io.read[0].bits.addr, 3) @[dcache.scala 280:38]
    smem array_0_0 : UInt<64>[1][512], undefined @[DescribedSRAM.scala 23:26]
    node _T_1 = bits(io.write.bits.way_en, 0, 0) @[dcache.scala 288:33]
    node _T_2 = and(_T_1, io.write.valid) @[dcache.scala 288:37]
    when _T_2 : @[dcache.scala 288:56]
      node _T_3 = bits(io.write.bits.data, 63, 0) @[dcache.scala 289:75]
      wire _T_4 : UInt<64>[1] @[dcache.scala 289:27]
      _T_4[0] <= _T_3 @[dcache.scala 289:27]
      node _T_5 = bits(io.write.bits.wmask, 0, 0) @[dcache.scala 290:54]
      write mport _T_6 = array_0_0[waddr], clock
      when _T_5 :
        _T_6[0] <= _T_4[0]
        skip
      skip @[dcache.scala 288:56]
    node _T_7 = bits(io.read[0].bits.way_en, 0, 0) @[dcache.scala 292:72]
    node _T_8 = and(_T_7, io.read[0].valid) @[dcache.scala 292:76]
    wire _T_9 : UInt @[dcache.scala 292:42]
    _T_9 is invalid @[dcache.scala 292:42]
    when _T_8 : @[dcache.scala 292:42]
      _T_9 <= _T @[dcache.scala 292:42]
      node _T_10 = or(_T_9, UInt<9>("h00")) @[dcache.scala 292:42]
      node _T_11 = bits(_T_10, 8, 0) @[dcache.scala 292:42]
      read mport _T_12 = array_0_0[_T_11], clock @[dcache.scala 292:42]
      skip @[dcache.scala 292:42]
    reg _T_13 : UInt, clock @[dcache.scala 292:31]
    _T_13 <= _T_12[0] @[dcache.scala 292:31]
    io.resp[0][0] <= _T_13 @[dcache.scala 292:21]
    smem array_1_0 : UInt<64>[1][512], undefined @[DescribedSRAM.scala 23:26]
    node _T_14 = bits(io.write.bits.way_en, 1, 1) @[dcache.scala 288:33]
    node _T_15 = and(_T_14, io.write.valid) @[dcache.scala 288:37]
    when _T_15 : @[dcache.scala 288:56]
      node _T_16 = bits(io.write.bits.data, 63, 0) @[dcache.scala 289:75]
      wire _T_17 : UInt<64>[1] @[dcache.scala 289:27]
      _T_17[0] <= _T_16 @[dcache.scala 289:27]
      node _T_18 = bits(io.write.bits.wmask, 0, 0) @[dcache.scala 290:54]
      write mport _T_19 = array_1_0[waddr], clock
      when _T_18 :
        _T_19[0] <= _T_17[0]
        skip
      skip @[dcache.scala 288:56]
    node _T_20 = bits(io.read[0].bits.way_en, 1, 1) @[dcache.scala 292:72]
    node _T_21 = and(_T_20, io.read[0].valid) @[dcache.scala 292:76]
    wire _T_22 : UInt @[dcache.scala 292:42]
    _T_22 is invalid @[dcache.scala 292:42]
    when _T_21 : @[dcache.scala 292:42]
      _T_22 <= _T @[dcache.scala 292:42]
      node _T_23 = or(_T_22, UInt<9>("h00")) @[dcache.scala 292:42]
      node _T_24 = bits(_T_23, 8, 0) @[dcache.scala 292:42]
      read mport _T_25 = array_1_0[_T_24], clock @[dcache.scala 292:42]
      skip @[dcache.scala 292:42]
    reg _T_26 : UInt, clock @[dcache.scala 292:31]
    _T_26 <= _T_25[0] @[dcache.scala 292:31]
    io.resp[0][1] <= _T_26 @[dcache.scala 292:21]
    smem array_2_0 : UInt<64>[1][512], undefined @[DescribedSRAM.scala 23:26]
    node _T_27 = bits(io.write.bits.way_en, 2, 2) @[dcache.scala 288:33]
    node _T_28 = and(_T_27, io.write.valid) @[dcache.scala 288:37]
    when _T_28 : @[dcache.scala 288:56]
      node _T_29 = bits(io.write.bits.data, 63, 0) @[dcache.scala 289:75]
      wire _T_30 : UInt<64>[1] @[dcache.scala 289:27]
      _T_30[0] <= _T_29 @[dcache.scala 289:27]
      node _T_31 = bits(io.write.bits.wmask, 0, 0) @[dcache.scala 290:54]
      write mport _T_32 = array_2_0[waddr], clock
      when _T_31 :
        _T_32[0] <= _T_30[0]
        skip
      skip @[dcache.scala 288:56]
    node _T_33 = bits(io.read[0].bits.way_en, 2, 2) @[dcache.scala 292:72]
    node _T_34 = and(_T_33, io.read[0].valid) @[dcache.scala 292:76]
    wire _T_35 : UInt @[dcache.scala 292:42]
    _T_35 is invalid @[dcache.scala 292:42]
    when _T_34 : @[dcache.scala 292:42]
      _T_35 <= _T @[dcache.scala 292:42]
      node _T_36 = or(_T_35, UInt<9>("h00")) @[dcache.scala 292:42]
      node _T_37 = bits(_T_36, 8, 0) @[dcache.scala 292:42]
      read mport _T_38 = array_2_0[_T_37], clock @[dcache.scala 292:42]
      skip @[dcache.scala 292:42]
    reg _T_39 : UInt, clock @[dcache.scala 292:31]
    _T_39 <= _T_38[0] @[dcache.scala 292:31]
    io.resp[0][2] <= _T_39 @[dcache.scala 292:21]
    smem array_3_0 : UInt<64>[1][512], undefined @[DescribedSRAM.scala 23:26]
    node _T_40 = bits(io.write.bits.way_en, 3, 3) @[dcache.scala 288:33]
    node _T_41 = and(_T_40, io.write.valid) @[dcache.scala 288:37]
    when _T_41 : @[dcache.scala 288:56]
      node _T_42 = bits(io.write.bits.data, 63, 0) @[dcache.scala 289:75]
      wire _T_43 : UInt<64>[1] @[dcache.scala 289:27]
      _T_43[0] <= _T_42 @[dcache.scala 289:27]
      node _T_44 = bits(io.write.bits.wmask, 0, 0) @[dcache.scala 290:54]
      write mport _T_45 = array_3_0[waddr], clock
      when _T_44 :
        _T_45[0] <= _T_43[0]
        skip
      skip @[dcache.scala 288:56]
    node _T_46 = bits(io.read[0].bits.way_en, 3, 3) @[dcache.scala 292:72]
    node _T_47 = and(_T_46, io.read[0].valid) @[dcache.scala 292:76]
    wire _T_48 : UInt @[dcache.scala 292:42]
    _T_48 is invalid @[dcache.scala 292:42]
    when _T_47 : @[dcache.scala 292:42]
      _T_48 <= _T @[dcache.scala 292:42]
      node _T_49 = or(_T_48, UInt<9>("h00")) @[dcache.scala 292:42]
      node _T_50 = bits(_T_49, 8, 0) @[dcache.scala 292:42]
      read mport _T_51 = array_3_0[_T_50], clock @[dcache.scala 292:42]
      skip @[dcache.scala 292:42]
    reg _T_52 : UInt, clock @[dcache.scala 292:31]
    _T_52 <= _T_51[0] @[dcache.scala 292:31]
    io.resp[0][3] <= _T_52 @[dcache.scala 292:21]
    io.nacks[0] <= UInt<1>("h00") @[dcache.scala 294:17]
